(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating (arch-shaped) air gaps as a low dielectric constant material between conductor lines.
(2) Description of the Prior Art
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The intra-dielectric material that is typically used to isolate conducting lines from each other is silicon dioxide, which is a thermally and chemically stable material. Continued decreasing of the horizontal dimensions of semiconductor devices leads to layers of metal that tend to have vertical dimensions that are not necessarily reduced accordingly resulting for instance in contact and via openings that have a high aspect ratio. Conventional oxide etching processes and materials are however available for such high aspect ratio contact and via openings. The dielectric constant of dense silicon oxide that is grown by thermal oxidation or by chemical vapor deposition is in the order of 3.9, CVD oxide has a relative dielectric constant of about 4.6. The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of slightly larger than 1.0. Dielectric constants of dielectric materials that can be used for intra-level or inter level dielectric material vary, typical values are for instance 4.1-4.5 for inorganic Plasma SiO.sub.2, 3.5 for inorganic fluorine doped SiO.sub.2 (FSG), 2.7-3.0 for Organic Polysilsequioxane (Si polymer), 2.7 for organic Bemzocyclobutene (BCB), etc.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. As the spacing between interconnect line patterns is reduced to the micron or sub-micron range, the parasitic intra-level capacitance between the lines increases. This increase in intra-level capacitance coupling results in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on the first conductor line alters or affects the voltage on the second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation while limiting the speed at which the device can operate. In many applications, the intra-level capacitance of the interconnect line pattern has become the limiting factor that determines the speed of gallium arsenide or silicon Integrated Circuits. It becomes therefore imperative to reduce the resistance-capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The intra-level capacitance between adjacent conducting lines is highly dependent on the insulator or dielectric used to separate the conducting lines. With the use of continuously decreasing line spacing between conducting lines, the low dielectric constants of the dielectric materials that are used are frequently not low enough to adequately off-set the effects of the decreased line spacing. In addition, the use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric materials in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing. The resulting interconnect structures may also reduce the efficiency of heat dissipation due to the fact that materials that have lower dielectric constants generally have lower thermal conductivity. Decreased spacing between lines in interconnect patterns may further cause concerns of reliability of the device due to such issues as electromigration, extremely high current density, failures of the wire pattern to adhere to underlying layers, the creation of mechanical stress patterns, etc.
To reduce the capacitive coupling and to thereby reduce capacitive crosstalk, a major objective in the design of IC's is to reduce the Dielectric Constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. The invention provides a method that introduces the use of an arch-shaped air gap between the interconnect lines.
U.S. Pat. No. 5,324,683 (Fitch et al.) teaches the formation of an air (FIGS. 13 to 17). The layers in Fitch differ in composition from the invention. This is close to the invention.
U.S. Pat. No. 3,689,992 (Schutze et al.) shows an air gap process using an etch back.
U.S. Pat. No. 5,750,415 (Gnade et al.) and U.S. Pat. No. 5,461,003 (Havemann et al.) show an air gap process using low-porosity silica film.
U.S. Pat. No. 5,641,712 (Grivna et al.) teaches an air gap process using a special deposition process.
U.S. Pat. No. 5,407,860 (Stoltz et al.) recites an air gap method using an etch back process.